For those that may be interested Andrew and I just finished a prototype of an S-100 bus "System Monitor Board". The board has the following features:-
HEX LED display of all Data and Address lines. At all times the address of the master (or slave) CPU's program counter is displayed as a Hex LED display. If an 8 bit CPU is controlling the bus the current 8 bit instruction it is reading is displayed. If a 16 bit CPU is currently the master the 16 bit bidirectional data bus is displayed. Note because most 16 bit CPU's pipeline their instructions the data in and address bus may be slightly ahead of the actual instruction the CPU is executing.
Hardware Breakpoint Switches. The board has a row of 20 small dip switches and circuitry such that if the CPU ever goes to a specified address it will stop. From there it can then be single stepped forward one CPU instruction at a time displaying the current 24 bit address and 8/16 bit data in being read on the bus. This is very useful for both hardware and software debugging. Unlike software debuggers it is memory location and CPU type independent. It will work anywhere in the 24 bit S-100 memory address space with a master or any slave CPU.
Stop and Single Step Circuitry. This circuitry allows one to stop the current running master CPU at any time and restart from that location again or single step the CPU forward one instruction at a time. It works with both 8 and 16 bit CPUs
Hardware Reset and Slave Clear Circuitry. In the past I have had problems with the length of time a low going reset signal was presented on the bus. For example the SD Systems 8024 Video board will not reset its onboard CRT controller in time if the signal is too short. It is also important to have a single sharp square wave reset signal for CPU's like the 80286. Finally many older S100 CPU boards do not have a Slave Clear option. For these reasons I have added two 555's to allow precise control of the S-100 Reset and Slave Clear functions. These can be triggered by push button switches.
An IOBYTE Port. This is a simple 8 bit switch/input port that allows the user to configure the consol, printer reader etc for IO in hardware. It's a carry over of the early Teletype days and was used in early versions of CPM, but it is useful is setting BIOS options because the data is not lost when the power is removed. The port can reside anywhere within the range of E8-EFH
Master/Slave Switching Circuitry. This is an input port that allows one to bring low the S-100 TMA0 or TMA1 bus lines, useful for CPU master/slave switching. The port can reside anywhere within the range of E8-EFH
A System Tick Clock. This is just a simple timer that allows one to pulse one of the S-100 interrupt lines ~10 times a second. This is useful for CPM-86 background processing and multi-user systems. Again a 555 time is used but the "normal" circuitry is modified (with a diode) to give a narrow sharp low going pulse which can be jumpered to any one of the S-100 vector interrupt lines V0-V7. The clock it reset by the S-100 INTA or by inputting from a port (one of E8H -EFH) via a jumper.
A 2MHz signal for the S-100 Bus line #49. This line is not often used but when it is, it is typically used for things like a UART baud rate generator. The IEEE-696 specs specify exactly and always 2MHz. Some older S-100 boards tap into the master CPU clock (4MHz) and divide by two. This limits these boards to being always used at 4MHz.
Inverse of the Master Clock signal (S-100 line #25). Some older S-100 boards count of the pSTVAL signal being a simple inverse of the main clock signal. The IEEE-696 signal is not exactly like this. The most well known example of this is the SD Systems Versafloppy II FDC board. There are modifications that can be made to that board to get it to work but the simplest thing to do is just supply the inverse clock signal on an unused S-100 bus line and redirect the Versafloppy to that line. I use the unused S-100 line #27, "RFU".
For more information about the board see:-