TRS-IDE http://www.qsl.net/zl1wjq/trside1.htm TRS IDE occupies 16 addresses 0x40-0x47, and a mirror at 0x48-0x4F (A3 is not connected). In this address space the IDE registers are mapped 1 to 1. The upper data register byte is unconnected. Occupied I/O addresses: 0x40 IDE data register 0x41 IDE error/feature register 0x42 IDE sector count register 0x43 IDE sector number register 0x44 IDE cylinder low register 0x45 IDE cylinder high register 0x46 IDE drive/head register 0x48 IDE command/status register GIDE http://www.gaby.de/gide/ and http://www.iee.et.tu-dresden.de/~kc-club/gide/gide.html The G-IDE occupies 12 addresses. The base address is configurable in 16 steps, so can be mapped in the whole I/O-space (address lines A4-A7). The 16 bit data register can be addressed with two 8-bit accesses (Z80 instructions INI and OTIR). The IDE registers are mapped from BASE+0x8 to BASE+0xF. The extra IDE addresses (alternate status/digital output register and IDE drive address register are mapped to 0x6 and 0x7. At 0x5 is the Real Time clock. 0x4 is decoded for expansion Occupied I/O addresses: 0x?4 reserved for IDE expansion board 0x?5 RTC access 0x?6 IDE alternate status / digital output register 0x?7 IDE drive address register 0x?8 IDE data register 0x?9 IDE error/feature register 0x?A IDE sector count register 0x?B IDE sector number register 0x?C IDE cylinder low register 0x?D IDE cylinder high register 0x?E IDE drive/head register 0x?F IDE command/status register (? is configurable from 0 to F) Conclusion: A driver written for the TRS-IDE, using only half of each 512-byte sector can be adapted for the GIDE, by writing a dummy byte during the second half of the block transfer. The disk could even be compatible between the two drivers! Using the full GIDE potential is possible only by rewriting a larger part of the driver. Reading is no problem, but writing will become slower ar the other half of the sector should be read first, the two halves combined and then written to disk. Buffer space is 768 bytes.