Information is from DAInamic 5 May-June 1981 page 115
1 | GROUND | SCREENING LINE |
2 | D0 | DATA BIT 0 |
3 | GROUND | SCREENING LINE |
4 | D1 | DATA BIT 1 |
5 | GROUND | SCREENING LINE |
6 | D2 | DATA BIT 2 |
7 | GROUND | SCREENING LINE |
8 | D3 | OATA BIT 3 |
9 | GROUND | SCREENING LINE |
10 | D4 | DATA BIT 4 |
11 | GROUND | SCREENING LINE |
12 | D5 | DATA BIT 5 |
13 | GROUND | SCREENING LINE |
14 | D6 | DATA BIT 6 |
15 | GROUND | SCREENING LINE |
16 | D7 | DATA BIT 7 |
17 | GROUND | SCREENING LINE |
18 | - | NO CONNECTION |
19 | GROUND | SCREENING LINE |
20 | MEMW | MEMORY WRITE STROBE |
21 | GROUND | SCREENING LINE |
22 | - | NO CONNECTION |
23 | A10 | ADDRESS LINE 10 |
24 | MEMR | MEMORY READ STROBE |
25 | A14 | ADDRESS LINE 14 |
26 | A11 | ADDRESS LINE 11 |
27 | A12 | ADDRESS LINE 12 |
28 | A13 | ADDRESS LINE 13 |
29 | A9 | ADDRESS LINE 9 |
30 | A15 | ADDRESS LINE 15 |
31 | A7 | ADDRESS LINE 7 |
32 | A8 | ADDRESS LINE 8 |
33 | A5 | ADDRESS LINE 5 |
34 | A6 | ADDRESS LINE 6 |
35 | A3 | ADDRESS LINE 3 |
36 | A4 | ADDRESS LINE 4 |
37 | A1 | ADDRESS LINE 1 |
38 | A2 | ADDRESS LINE 2 |
39 | A0 | ADDRESS LINE 0 |
40 | INTA | INTERRUPT ACKNOWLEDGE |
41 | CS LOW ROM | CHIP SELECT LOWER ROM |
42 | CS LB UPP ROM | CHIP SELECT LOWER BANK UPPER ROM |
43 | PSEUDO A12 | A12 AFTER START-LOGIC |
44 | CS UB UPP ROM | CHIP SELECT UPPER BANK UPPER ROM |
45 | +5V | 5 VOLT |
46 | +5V | 5 VOLT |
47 | RAMOP | NOT RAM OPERATION |
48 | CK2 | TTL LEVEL CLOCK (2MHz) |
49 | HOLD | HOLD REQUEST |
50 | SYNC | CPU SYNC SIGNAL |